(a) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, in particular to a process for forming trenches in different depths at a cell region and a peripheral region for reducing SAS resistance at the cell region.
(b) Description of the Related Art
Recently, as flash memories are widely utilized and price competition grows, various technologies have been developed for reducing the sizes of the devices. One of those is a self aligned source (SAS) technique.
The SAS technique is a method for reducing the cell size in a bit line direction and is essentially adopted for below-0.25 μm line width technology since it can reduce a gap between the gate and the source such that the cell size can be reduced about 20% with the introduction of the SAS technique.
However, the conventional SAS technique has a drawback in that contact resistance of the source per cell dramatically increases because the SAS region is formed along the trench profile.
In the meantime, the below-0.25 μm or below-0.18 μm technology is utilized together with a shallow trench isolation (STI) technique for fabricating the most semiconductor devices.
That is, the STI technique and the SAS technique are essential to reduce the cell size in a word line direction and a bit line direction, respectively. However, simultaneous adaptation of these two techniques causes to dramatically increase the source resistance.
Especially, in case of the flash memory the reduction of the cell size causes to increase the depth of the trench since it uses high internal voltage, resulting in deterioration of the source resistance.
FIG. 1 is a graph illustrating variation of the source resistance according to a trench depth. As shown in FIG. 1, in case of the trench depth of 2400 Å the resistance per cell is 510 Ohm. In the meantime, in case of 3600 Å the resistance per cell becomes about 880 Ohm.
Conventional flash memory and SAS-related technologies have been disclosed in the U.S. Pat. No. 6,306,737, the U.S. Pat. No. 6,436,765, and the U.S. Pat. No. 5,120,671.
Since the trench depth of the 0.18 technology flash memory cell is 3500 Å, it dramatically degrades the source resistance. In order to solve this problem, mask processes for forming isolation structures are separately carried out at the cell region and the peripheral region.
In this method, the trenches are formed at different depths for the cell region and the peripheral region. For example, the trench is formed at a depth of about 3500 Å for the cell region and at a shallow depth of about 1800 Å for the peripheral.
In order to form the trenches at different depths for the cell and peripheral regions, a photolithography process using a deep ultra violet (DUV) light source is separately adopted at the cell region and the peripheral region.
The conventional technique will be described hereinafter with reference to the accompanying drawings.
As shown in FIG. 2a, firstly, a pad oxide layer 110, a pad nitride layer 120, and a dielectric layer 130 which is used as a hard mask are sequentially deposited on a semiconductor substrate 100. In order to simplify the explanation, the semiconductor substrate 100 is divided into a cell region (C) and a peripheral region (P).
Next, in order to form a trench a first DUV photoresist pattern 140 is prepared in a state that the entire peripheral region (P) is blocked and the cell region (C) is exposed at a predetermined width.
Next, as shown in FIG. 2b, one trench (Tc) is formed by sequentially etching the dielectric layer 130, the pad nitride layer 120, the pad oxide layer 110, and the semiconductor substrate 100 in the cell region exposed using the first DUV photoresist pattern 140 as a mask. The trench (Tc) is formed inside the cell region at a required shallow depth.
Next, as shown in FIG. 2c, another trench (Tp) is formed by sequentially etching the dielectric layer 130, the pad nitride layer 120, the pad oxide layer 110, and the semiconductor substrate 100 in the peripheral region (P) exposed using a second DUV photoresist pattern 150 which blocks the entire cell region (C).
Here, the trench (Tp) which is formed in the peripheral region (P) is formed so as to be deeper than the trench (Tc) formed in the cell region (C).
In this conventional method using the DUB light source, the etching process is applied to the cell and peripheral regions separately using the first and second DUV photoresist patterns, respectively.
However, the conventional method has drawbacks in that the mask or reticle and the photoresist, which are used for a fine linewidth processing technique with the short wavelength such as DUV in the isolation process, are very expensive so as to increase the entire manufacturing costs. Accordingly, it is required to develop an improved technique for reducing the manufacturing costs.